The ongoing trend of increasing the density of semiconductors in order to answer to today's need for ultra-large scale integrated (ULSI) semiconductor devices has led to the urgency of advanced monitoring and quality control of each and every step of the semiconductor manufacturing process. Particularly, the monitoring of the photolithographic step is becoming increasingly important.
There follows a description of prior art that is related to the photolithographic process.
After creation of polysilicon, crystal pulling, wafer slicing, lapping and polishing, and after wafer epitaxial processing (for more details, attention is directed to the semiconductor manufacturing process on the Fullman Company Website [3]), the wafer is transported to the lithography station.
Resist coating, development, alignment and exposure are the main steps in the photolithographic process that transfers the circuit pattern for one layer from a photomask or reticle onto the light-sensitive photoresist on the wafer surface.
Attention is directed to FIG. 1, which is a schematic representation of a typical track where the lithography steps are performed.
The track 10 is in principal, a platform on which a multiple of stations that perform specific tasks are situated. The wafer is usually part of a batch of wafers, loaded in a cassette, containing a number (e.g. 25 units) of wafers.
The cassette is loaded onto the track at the loading station 11. From here, a centralized robotic arm 12 will move one wafer at the time from one station to another station under the control of a “recipe” or computer program that defines the procedures a wafer has to undergo during the photolithography.
At the onset, the robotic arm transports the wafer to the center alignment station 13. Here, the wafer is precisely positioned to ensure the wafer is situated concentrically. (Optionally, the wafer is returned at various points during the photolithographic step back to this station for critical re-alignment). The wafer is then transported to a cleaning station 14, to ensure maximum surface cleanness before being moved to the coating station 15. Here the photoresist is deposited on the wafer in a predefined amount of viscous fluid. The photoresist is thinly distributed evenly over the total surface of the wafer by means of fast spinning. The wafer is then transported optionally to a pre-baking station. The pre-baking is in effect a thermal oven that hardens the still very soft photoresist layer. In the stepper 17 the image of the mask or reticle is projected onto the wafer using actinic light (UV, usually UV of very short wavelength—“deep-UV” or DUV), thus exposing the photoresist. The wafer is then moved in the stepper in either or both x- and y-directions by a pre-defined number of “steps” (hence the name “Stepper”). This process is being repeated as many times as number of dies that are to be positioned on the wafer (step and repeat). The wafer is then transported back to the track to the developing station 18 where an acid or base solution is used to remove those parts of the photoresist that became soluble by exposure. The wafer is then subjected to metrology inspection by transporting a wafer to be inspected to the unloading station 20 and from there to the stand alone inspection station. Should the inspection result in detection of defects, errors or misalignments, the wafer is optionally returned to the loading station 11 of the track from where the wafer is transported to the stripping station 21. Here a suitable solvent removes the photoresist layer. The wafer can then be transported back to the alignment 13 or cleaning station 14 for “rework” (e.g. the process of repeating the previous, not successful manufacture steps). The following optional step is another baking station 19, also called post-baking station where further hardening of the remaining photoresist layer occurs. The manufacturing steps that follow the photolithography are not further discussed here, as they are not relevant to the present invention.
There follows now a description of the metrology inspection used in the prior art.
Attention is directed to FIG. 2, which is a schematic representation of OL and CD measurement procedures, according to the prior art.
Two metrology inspection methods that are commonly used to determine the quality of the photolithography step are:
    1. The overlay (OL) inspection measures the registration of consecutive layers of multiple-layer semiconductor chips. During the OL inspection, a wafer is extracted from the stepper 23 and moved to an optical microscope 24 where the position of marks or targets of the previous processed layer are measured against the marks of the layer that is currently being added.    2. The Critical Dimension (CD) inspection measures line-widths of the layer. During the CD inspection, a wafer is extracted from the track 25 and moved to a high-resolution CD-SEM 26, where the line width is measured and determined to be within pre-determined tolerances. The arrows 27 indicate the transportation from the stepper and track to the inspection tools and back.
There follows now a description of the Related Art of how a known per se CD-SEM may be used by means of example of checking CD with the help of a FEM.
In the fabrication of semiconductor devices, photolithographic masks are used to transfer circuitry patterns to silicon wafers in the creation of integrated circuits. In general, in the production of semiconductor circuit devices, a series of such masks are employed in a preset sequence.
Each photolithographic mask includes an intricate pattern of CAD-generated geometric patterns corresponding to the circuit components to be integrated onto the wafer. Each mask in the series is used to transfer its corresponding pattern onto a photosensitive layer (photoresist) which has been previously deposited on the silicon wafer. The transfer of the mask pattern onto the photosensitive layer or photoresist is currently performed by an optical exposure tool, which directs light or radiation through the mask to the photoresist.
Fabrication of the photolithographic mask follows a set of predetermined design rules, which are set by processing and design limitations. For example, these design rules define the space tolerance between devices or interconnecting lines, and the width of the lines themselves, to ensure that the devices or lines do not overlap or interact with one another in undesirable ways. The design rule limitation is referred to within the industry as the “CD” (critical dimension). The critical dimension of a circuit is defined as the smallest width of a line or the smallest space between two lines, which is to be permitted in the fabrication of the chip. More often than not, the CD is determined by the resolution limit of the exposure equipment. Presently, the CD for most applications is on the order of a fraction of a micron. Because of the extremely small scale of the CD, the instrument of choice for measurement and inspection is a scanning electron microscope (SEM).
When new masks are produced, or after any change in the fabrication recipe, it is customary to form a so-called focus exposure matrix (FEM) on a test wafer in order to obtain the best exposure/focus combination for the masks e.g., the combination of focus and exposure which results in the best resolution on the wafer, in keeping with the required CD. This is typically done by, for example, sequentially exposing a series of areas of the wafer with the pattern of the mask, while exposure and focus values are incrementally changed from one exposure location to the next. After exposure of the wafer in this fashion, one can examine the individual exposure sites, for example, to check the CD, and obtain a plot of exposure v. focus or focus v. CD and determine the area of best performance from the resulting curves. Specifically, a test wafer is exposed in a stepper while the focus is varied along one axis and the exposure is varied along the other. Thus, a matrix of images is obtained on the exposed wafer, wherein each exposure site or die has a different focus-exposure setting. Selected CDs (at various locations) in each die are measured to select the best exposure-focus setting for the particular mask.
The general procedure for determining the CD in a test wafer is as follows. First, an alignment target (which is not part of the circuitry) is included on the mask, typically at an area, which will not include circuit patterns. During exposure, an image of the alignment target is transferred onto each of the dies. When the test wafer is developed and loaded into the CD measurement machine (typically a CD SEM) the operator first causes he system to acquire the alignment target of the central or reference die of the wafer. The image of this alignment target is stored in memory for reference. The operator then acquires an appropriate area for CD measurement, and designates that area to the CD machine. The machine automatically calculates a vector from the center of the alignment target to the center of the designated area. This procedure is repeated for each area, which the operator wishes to measure. The foregoing procedure can be performed in what might be designated as a “teaching mode” of the CD SEM. Once all of the data has been input and the vectors calculated, the CD system might then be enabled for automated CD measurement as described below.
When the developed wafer is properly loaded into the CD machine, the machine moves to the first die to be inspected and searches for the alignment target using a pattern recognition (PR) algorithm, using the aforementioned stored alignment target as a reference. When a high PR score is achieved, it is considered that the alignment target has been acquired. Using the stored vector, the CD machine then moves to the designated CD measurement site and acquires an image for CD measurement, which is then performed. Following this procedure, which may be duplicated for other locations on the die, the CD machine then goes to the next die and again using the PR algorithm searches for the alignment target using the stored target as a reference. Once a high PR score is achieved, the CD machine goes to the CD measurement site using the stored vector. This process is repeated until all of the designated dies have been measured.
After having described an example of CD-SEM usage, prior art limitations of OL and CD procedures are discussed.
In prior art, the inspection of a batch of wafers during the photolithograpy step has been executed on a sampling bases only, due to the inherent prolonged and cumbersome process of inspection, which necessitates actual removal of the inspection wafer from the track and feeding the wafer to the overlay machine. (The latter naturally requires preliminary set-up and alignment steps in order to assure that the wafer is accurately placed before the overlay procedure commences. The same applies to the operation of the CD-SEM.
It was accordingly accepted that if no errors were detected in the sample wafer then, the other wafers in the batch were also without problems.
Thus, the batch was transferred to the consecutive steps in the manufacturing process, i.e. etching, deposition or ion implantation. At this point any further processing would represent a point of “no return” in the whole chain of manufacturing steps. Until this point, the detection of errors or defects would initiate a “rework” process that includes stripping the resist coating off the wafers, and returning the wafers to the beginning of the photolithographic step. Except for some decrease in throughput, and minimal waste of photoresist coating, exposure means and developer, no further damage occurred. To show the importance of monitoring the photolithographic step, a worst-case scenario would describe the adding of the last layer of a multi-layer semiconductor while errors or defects are introduced undetected, and proceeding with the following step. Up and until this point, the previous step is reversible, if said errors or defects were detected by inspection at this point, thus preserving all previous layers and the time and materials it took to manufacture them. It is of importance to mention that due to the fact that wafers are inspected only by sample, the loss of time and materials can accumulate to significant proportions, as detection of errors or defects is usually executed after a batch of wafers has completed the photolithographic step. Thus, in case of errors or defects, all wafers of the batch exhibited the same problem. By not inspecting each wafer individually, errors or defects were repeatedly produced.
Some issues that are not being addressed by prior art procedures of OL and CD inspection:    1. By using the sampling method, no data is being generated about the rest of the wafers in the same batch.    2. The handling of samples from the track to the stand-alone OL or CD-SEM apparatus is time consuming and can introduce contamination and mechanical damage due to wafer handling. (FIG. 2).    3. The number of available inspection tools per photolithographic station, typically about one OL tool per four photolithographic stations, causes bottleneck situations, which substantially adversely affect throughput.    4. The introduction of advanced photomasks for subwavelength (beyond 0.25 micron) integrated circuit (IC) manufacturing, reaching the envelope of optical OL capabilities, thus bringing about a substantial decrease of optical image quality, and consequently, rendering the conventional OL tools less and less useful.    5. The increasingly frequent use of CMP (Chemical Mechanical Planarization—a technique to flatten the surface of the added layers of conductive or insulating materials) induces low-contrast images, which lowers the accuracy of optical OL measurement systems. This flattening reduces the average height of a layer-line to approach the envelope of optical OL capabilities, thus bringing about a substantial decrease of optical image quality. It is important to notice that the current trend of even more reduction of average height of layer lines will go beyond the envelope of optical OL capabilities, thus severely limiting the conventional optical OL tools.    6. Contamination of wafer due to exposure to electron beam when a sample is being objected to CD-SEM inspection.    7. Submitting the wafer to vacuum during the CD-SEM inspection is a time consuming step, using complex equipment and setup.    8. TIS (Tool Introduced Shift) errors of optical microscope in OL measurements.
Although both overlay and CD monitoring measurements are similar in the metrology used, there has been no prior art solutions found for using one and the same tool for both tasks. Moreover, it is not apparent how to go about combining both tasks since traditional CD-SEM and overlay equipment have different requirements (e.g., electron optics and vacuum for CD-SEM and light optics with no vacuum for overlay).
Due to sever space limitations traditional CD-SEM and/or overlay cannot be placed in the track.
Current overlay and CD-SEM systems are designed to provide absolute measurements. For monitoring a production line however, it may be sufficient only to monitor changes even if the absolute values are unavailable.
There is accordingly a need in the art to provide for a system that substantially reduces or eliminates the limitations in hitherto known solutions. In particular, there is a need in the art to incorporate OL and/or CD measurements within the track on a one-to-one sampling bases (necessitating NDT—Non Destructive Testing—mode), thereby obtaining overall throughput increase, and a higher yield.